The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a diagnostic function.
A semiconductor integrated circuit device is required to be excellent in mass productivity, and to have high reliability on the basis of a fault detectability approximately equal to 100%. However, in a semiconductor integrated circuit device having as many as thousands of or tens of thousands of gates, it is almost impossible to enhance the fault detectability only by using a test pattern, and it is necessary to provide some diagnostic circuit in the device.
The diagnostic circuit is usually constructed as follows. That is, flip-flops in an integrated circuit have the master-slave structure and are connected to each other so as to form shift registers, external data are successively applied to the flip-flops through a pad, and internal data of the flip-flops are successively read out, to detect the presence or absence of a fault.
Conventional diagnostic circuits of this kind are depicted in FIG. 7 of U.S. Pat. No. 3,761,695, FIGS. 4, 6 and 7 of U.S. Pat. No. 4,051,352, FIG. 7 of U.S. Pat. No. 4,063,080, FIGS. 4 and 7 of U.S. Pat. No. 4,074,851, and an article entitled "A Logic Design Structure for LSI Testability" by E. B. Eicherberger (14th DA Conference, 1977, pages 462 through 468). The prior art shown in these publications will be explained below, with reference to FIG. 1.
FIG. 1 shows a semiconductor integrated circuit device including an RS flip-flop 19. Referring to FIG. 1, the flip-flop 19 is made up of two-input NAND gates 20 and 21, and a diagnostic circuit which includes two-wired, two-input AND/NOR gates 25 and 26, and inverters 27 and 28. The gates 25 and 26 have a set terminal SO, a reset terminal RO for logical operation, a terminal 29 for diagnostic mode signal, a terminal 30 for diagnostic data signal, and terminals 29' and 30' for inverted signals of the signals from the terminals 29 and 30.
When the signal applied to the terminal 29 is at the logical level of "1", the device shown in FIG. 1, performs an ordinary logical operation. On the other hand, when the signal applied to the terminal 29 is at the logical level of "0", the outputs RO and SO of the gates 25 and 26 take the same logical levels as those of terminals 30 and 30', respectively. Thus, a diagnostic data signal supplied to the terminal 30 is applied to the flip-flop 19. In other words, the gates 25 and 26 operate as a two-input multiplexer, and select one of an ordinary logical input or a diagnostic input in accordance with the logical level at the terminal 29.
In the case where such a flip-flop cell (including the flip-flop 19 and diagnostic circuit) is formed of CMOS gates, the cell requires seven gates in terms of two-input NAND gate (hereinafter the number of gates will be calculated in terms of two-input NAND gate). That is, the number of gates included in the above cell is larger than the number of gates included in the flip-flop 19 by five. As is well known, a two-input NAND CMOS gate is formed of two pairs of PMOS and NMOS transistors having a common gate electrode (that is, four MOS transistors). The number of gates calculated in terms of two-input NAND gate is readily obtained by dividing the number of inputs of the gates by two.
Another example of such a prior art is disclosed in U.S. Pat. application Ser. No. 575,706 (corresponding to Japanese Patent Application Appl. No. 58-16045). This example will be explained below, with reference to FIG. 2.
A device shown in FIG. 2 is made up of a D-type flip-flop 1, two-wired two-input AND/NOR gates 3 and 4, an AND gate 2, an inverter 5, a D-type flip-flop 6, and a three-state buffer 7.
The D-type flip-flop 1 has a circuit configuration shown in FIG. 3, and is made up of three-input NAND gates 31 and 32, inverters 33 and 34 for inverting the outputs of the gates 31 and 32, three-input NAND gates 35 and 36 for controlling an input D and an input T, and an inverter 37.
The truth table of the flip-flop 1 is shown in the following table.
TABLE 1 ______________________________________ Terminal State .sup.--S .sup.--R D T Q .sup.--Q ______________________________________ 1 0 0 -- -- 0 0 2 0 1 -- -- 1 0 3 1 0 -- -- 0 1 4 1 1 -- 0 Q.sub.n-1 ##STR1## 5 1 1 0 ##STR2## 0 1 6 1 1 1 ##STR3## 1 0 ______________________________________
The master-slave type circuit construction, excluding the three-state buffer 7, shown in FIG. 2 permits a loop connection for returning the output of the flip-flop 1 to the input through a combinational circuit, and makes it possible to transfer the output data of combination sections to the flip-flop at one clock timing.
According to the above circuit construction, when an input signal having the logical level of "1" is applied to a terminal 8, an ordinary logical operation is performed. When the terminal 8 is at the logical level of "0", a diagnostic data signal supplied to a terminal 9 is transferred to an input terminal S of the flip-flop in synchronism with a strobe pulse signal supplied to a terminal 10. The signal from the terminal 14 for a diagnostic reset signal is inputted to an input terminal R.
According to the above prior art, the number of gates included in the flip-flop element is equal to 13.5, and is larger than the number of gates included in the flip-flop of FIG. 3 by six. Moreover, as the control operation for diagnostic becomes complicated, the number of gates connected to the input side of the flip-flop is increased. Thus, the response time of the flip-flop element becomes long.
As can be seen from the above, various diagnostic circuits which have hitherto been used, make large the scale of an integrated circuit in a chip, and thus reduce the integration density substantially. Specifically, in a gate array device, the above diagnostic circuits considerably reduce the number of effective circuit elements since a available number of gates in a semiconductor chip is predetermined.
Further, as the diagnostic circuit becomes complicated, the response time of a flip-flop cell becomes long, as explained above.
The term "gate array LSI" means a large scale integrated circuit, on which only a wiring pattern is formed by using masks corresponding to a desired circuit configuration, to produce an integrated circuit having a desired circuit operation. According to such a method, semiconductor wafers in which various processes preceding a wiring process have been completed, are stocked and then used for fabricating various integrated circuit devices. Thus, the fabrication time and cost are greatly reduced.